Phase-Locked Loops & Frequency Synthesis
A phase-locked loop (PLL) is a feedback system that synchronises an oscillator to a reference signal in both frequency and phase. PLLs are ubiquitous in RF systems: they generate the local oscillator frequency in every radio receiver and transmitter, provide clock recovery in serial data links, and clean up noisy frequency sources.
PLL Building Blocks
| Block | Function | Key parameter |
|---|---|---|
| Phase detector (PD) / PFD | Compares phase of reference and divided VCO output. Generates error signal. | Gain K_φ (A/rad or V/rad) |
| Charge pump (CP) | Converts PFD pulses to current. Charges loop filter. | Current I_CP (µA–mA) |
| Loop filter (LF) | Integrates CP output. Sets loop bandwidth and stability. | Bandwidth f_n, phase margin |
| VCO | Voltage-controlled oscillator. Output frequency ∝ control voltage. | Gain K_VCO (MHz/V) |
| Divider ÷N | Divides VCO frequency by N to match reference. N sets output frequency. | Division ratio N |
How It Works
The PFD compares the phase of the reference (f_ref) to the divided VCO output (f_VCO/N). When they match, the loop is locked and f_VCO = N × f_ref. If the VCO drifts high, the PFD generates a correction signal that reduces the control voltage, pulling the frequency back. The loop bandwidth determines how fast this correction happens.
Open-Loop Transfer Function
where F(s) is the loop filter transfer function. The loop bandwidth f_n is approximately where |G(jω)| = 1. Phase margin should be 45–60° for stable, well-damped response.
Lock Time and Bandwidth Tradeoff
The loop bandwidth controls a fundamental tradeoff:
- Wide bandwidth: Fast lock time, good VCO noise suppression, poor reference spur rejection, more reference noise passes through.
- Narrow bandwidth: Slow lock time, poor VCO noise suppression at close-in offsets, excellent reference spur rejection.
Typical loop bandwidths: 1–100 kHz for frequency synthesisers, 1–10 MHz for fast-hopping systems.
Phase Noise in a PLL
Inside the loop bandwidth, the PLL output tracks the reference and the output phase noise follows the reference noise amplified by 20·log₁₀(N). Outside the loop bandwidth, the output phase noise equals the free-running VCO phase noise. The total output phase noise is the worst of the two at each offset:
Integer-N vs Fractional-N
| Architecture | Channel spacing | Phase noise | Reference spurs |
|---|---|---|---|
| Integer-N | = f_ref | 20·log(N) above reference noise | Low |
| Fractional-N (Σ-Δ) | < f_ref (any) | Higher N → worse noise; Σ-Δ adds quantisation noise | Fractional spurs |
Integer-N synthesis requires f_ref = channel spacing. For a 200 kHz GSM channel with a 200 kHz reference, the division ratio N can be 4000–9000 for 800–1800 MHz output — the 20·log₁₀(N) penalty is 72–79 dB above the reference noise. Fractional-N uses a Σ-Δ modulator to rapidly switch between integer values of N, achieving fractional average division ratios and allowing wider f_ref for better phase noise.
Reference Spurs
Reference spurs are discrete spectral lines in the VCO output at offsets of ±f_ref (and harmonics) from the carrier. They arise from imperfect charge pump matching — leakage current causes small periodic control voltage ripples at the reference rate. Typical specification: < −70 dBc. Reference spurs cause interference to adjacent channels.
Practical PLL Design Steps
- Choose f_ref = GCD of all required output frequencies (integer-N) or use fractional-N for fine frequency resolution.
- Select VCO with adequate tuning range, low K_VCO (for low sensitivity to supply noise), and target phase noise.
- Choose loop bandwidth: 1/10 of f_ref as a starting point to reject reference spurs.
- Design a 3rd or 4th order loop filter (2 poles, 1–2 zeros) for 50° phase margin.
- Simulate phase noise, lock time, and spur levels before fabricating.